#include <WProgram.h>
#include <Adafruit_I2CDevice.h>

Classes
class	Adafruit_TCS34725
	Class that stores state and functions for interacting with TCS34725 Color Sensor. More...

Macros
#define	TCS34725_ADDRESS (0x29)

#define	TCS34725_COMMAND_BIT (0x80)

#define	TCS34725_ENABLE (0x00)

#define	TCS34725_ENABLE_AIEN (0x10)

#define	TCS34725_ENABLE_WEN (0x08)

#define	TCS34725_ENABLE_AEN (0x02)

#define	TCS34725_ENABLE_PON (0x01)

#define	TCS34725_ATIME (0x01)

#define	TCS34725_WTIME (0x03)

#define	TCS34725_WTIME_2_4MS (0xFF)

#define	TCS34725_WTIME_204MS (0xAB)

#define	TCS34725_WTIME_614MS (0x00)

#define	TCS34725_AILTL (0x04)

#define	TCS34725_AILTH (0x05)

#define	TCS34725_AIHTL (0x06)

#define	TCS34725_AIHTH (0x07)

#define	TCS34725_PERS (0x0C)

#define	TCS34725_PERS_NONE (0b0000)

#define	TCS34725_PERS_1_CYCLE (0b0001)

#define	TCS34725_PERS_2_CYCLE (0b0010)

#define	TCS34725_PERS_3_CYCLE (0b0011)

#define	TCS34725_PERS_5_CYCLE (0b0100)

#define	TCS34725_PERS_10_CYCLE (0b0101)

#define	TCS34725_PERS_15_CYCLE (0b0110)

#define	TCS34725_PERS_20_CYCLE (0b0111)

#define	TCS34725_PERS_25_CYCLE (0b1000)

#define	TCS34725_PERS_30_CYCLE (0b1001)

#define	TCS34725_PERS_35_CYCLE (0b1010)

#define	TCS34725_PERS_40_CYCLE (0b1011)

#define	TCS34725_PERS_45_CYCLE (0b1100)

#define	TCS34725_PERS_50_CYCLE (0b1101)

#define	TCS34725_PERS_55_CYCLE (0b1110)

#define	TCS34725_PERS_60_CYCLE (0b1111)

#define	TCS34725_CONFIG (0x0D)

#define	TCS34725_CONFIG_WLONG (0x02)

#define	TCS34725_CONTROL (0x0F)

#define	TCS34725_ID (0x12)

#define	TCS34725_STATUS (0x13)

#define	TCS34725_STATUS_AINT (0x10)

#define	TCS34725_STATUS_AVALID (0x01)

#define	TCS34725_CDATAL (0x14)

#define	TCS34725_CDATAH (0x15)

#define	TCS34725_RDATAL (0x16)

#define	TCS34725_RDATAH (0x17)

#define	TCS34725_GDATAL (0x18)

#define	TCS34725_GDATAH (0x19)

#define	TCS34725_BDATAL (0x1A)

#define	TCS34725_BDATAH (0x1B)

#define	TCS34725_INTEGRATIONTIME_2_4MS (0xFF)

#define	TCS34725_INTEGRATIONTIME_24MS (0xF6)

#define	TCS34725_INTEGRATIONTIME_50MS (0xEB)

#define	TCS34725_INTEGRATIONTIME_60MS (0xE7)

#define	TCS34725_INTEGRATIONTIME_101MS (0xD6)

#define	TCS34725_INTEGRATIONTIME_120MS (0xCE)

#define	TCS34725_INTEGRATIONTIME_154MS (0xC0)

#define	TCS34725_INTEGRATIONTIME_180MS (0xB5)

#define	TCS34725_INTEGRATIONTIME_199MS (0xAD)

#define	TCS34725_INTEGRATIONTIME_240MS (0x9C)

#define	TCS34725_INTEGRATIONTIME_300MS (0x83)

#define	TCS34725_INTEGRATIONTIME_360MS (0x6A)

#define	TCS34725_INTEGRATIONTIME_401MS (0x59)

#define	TCS34725_INTEGRATIONTIME_420MS (0x51)

#define	TCS34725_INTEGRATIONTIME_480MS (0x38)

#define	TCS34725_INTEGRATIONTIME_499MS (0x30)

#define	TCS34725_INTEGRATIONTIME_540MS (0x1F)

#define	TCS34725_INTEGRATIONTIME_600MS (0x06)

#define	TCS34725_INTEGRATIONTIME_614MS (0x00)

Enumerations
enum	tcs34725Gain_t { TCS34725_GAIN_1X = 0x00, TCS34725_GAIN_4X = 0x01, TCS34725_GAIN_16X = 0x02, TCS34725_GAIN_60X = 0x03 }

Detailed Description

Software License Agreement (BSD License)

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ TCS34725_ADDRESS

#define TCS34725_ADDRESS (0x29)

I2C address

◆ TCS34725_COMMAND_BIT

#define TCS34725_COMMAND_BIT (0x80)

Command bit

◆ TCS34725_ENABLE

#define TCS34725_ENABLE (0x00)

Interrupt Enable register

◆ TCS34725_ENABLE_AIEN

#define TCS34725_ENABLE_AIEN (0x10)

RGBC Interrupt Enable

◆ TCS34725_ENABLE_WEN

#define TCS34725_ENABLE_WEN (0x08)

Wait Enable - Writing 1 activates the wait timer

◆ TCS34725_ENABLE_AEN

#define TCS34725_ENABLE_AEN (0x02)

RGBC Enable - Writing 1 actives the ADC, 0 disables it

◆ TCS34725_ENABLE_PON

#define TCS34725_ENABLE_PON (0x01)

Power on - Writing 1 activates the internal oscillator, 0 \ disables it

◆ TCS34725_ATIME

#define TCS34725_ATIME (0x01)

Integration time

◆ TCS34725_WTIME

#define TCS34725_WTIME (0x03)

Wait time (if TCS34725_ENABLE_WEN is asserted)

◆ TCS34725_WTIME_2_4MS

#define TCS34725_WTIME_2_4MS (0xFF)

WLONG0 = 2.4ms WLONG1 = 0.029s

◆ TCS34725_WTIME_204MS

#define TCS34725_WTIME_204MS (0xAB)

WLONG0 = 204ms WLONG1 = 2.45s

◆ TCS34725_WTIME_614MS

#define TCS34725_WTIME_614MS (0x00)

WLONG0 = 614ms WLONG1 = 7.4s

◆ TCS34725_AILTL

#define TCS34725_AILTL (0x04)

Clear channel lower interrupt threshold (lower byte)

◆ TCS34725_AILTH

#define TCS34725_AILTH (0x05)

Clear channel lower interrupt threshold (higher byte)

◆ TCS34725_AIHTL

#define TCS34725_AIHTL (0x06)

Clear channel upper interrupt threshold (lower byte)

◆ TCS34725_AIHTH

#define TCS34725_AIHTH (0x07)

Clear channel upper interrupt threshold (higher byte)

◆ TCS34725_PERS

#define TCS34725_PERS (0x0C)

Persistence register - basic SW filtering mechanism for \ interrupts

◆ TCS34725_PERS_NONE

#define TCS34725_PERS_NONE (0b0000)

Every RGBC cycle generates an interrupt

◆ TCS34725_PERS_1_CYCLE

#define TCS34725_PERS_1_CYCLE (0b0001)

1 clean channel value outside threshold range generates an \ interrupt

◆ TCS34725_PERS_2_CYCLE

#define TCS34725_PERS_2_CYCLE (0b0010)

2 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_3_CYCLE

#define TCS34725_PERS_3_CYCLE (0b0011)

3 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_5_CYCLE

#define TCS34725_PERS_5_CYCLE (0b0100)

5 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_10_CYCLE

#define TCS34725_PERS_10_CYCLE (0b0101)

10 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_15_CYCLE

#define TCS34725_PERS_15_CYCLE (0b0110)

15 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_20_CYCLE

#define TCS34725_PERS_20_CYCLE (0b0111)

20 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_25_CYCLE

#define TCS34725_PERS_25_CYCLE (0b1000)

25 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_30_CYCLE

#define TCS34725_PERS_30_CYCLE (0b1001)

30 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_35_CYCLE

#define TCS34725_PERS_35_CYCLE (0b1010)

35 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_40_CYCLE

#define TCS34725_PERS_40_CYCLE (0b1011)

40 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_45_CYCLE

#define TCS34725_PERS_45_CYCLE (0b1100)

45 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_50_CYCLE

#define TCS34725_PERS_50_CYCLE (0b1101)

50 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_55_CYCLE

#define TCS34725_PERS_55_CYCLE (0b1110)

55 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_PERS_60_CYCLE

#define TCS34725_PERS_60_CYCLE (0b1111)

60 clean channel values outside threshold range generates an \ interrupt

◆ TCS34725_CONFIG

#define TCS34725_CONFIG (0x0D)

Configuration

◆ TCS34725_CONFIG_WLONG

#define TCS34725_CONFIG_WLONG (0x02)

Choose between short and long (12x) wait times via \ TCS34725_WTIME

◆ TCS34725_CONTROL

#define TCS34725_CONTROL (0x0F)

Set the gain level for the sensor

◆ TCS34725_ID

#define TCS34725_ID (0x12)

0x44 = TCS34721/TCS34725, 0x4D = TCS34723/TCS34727

◆ TCS34725_STATUS

#define TCS34725_STATUS (0x13)

Device status

◆ TCS34725_STATUS_AINT

#define TCS34725_STATUS_AINT (0x10)

RGBC Clean channel interrupt

◆ TCS34725_STATUS_AVALID

#define TCS34725_STATUS_AVALID (0x01)

Indicates that the RGBC channels have completed an integration \ cycle

◆ TCS34725_CDATAL

#define TCS34725_CDATAL (0x14)

Clear channel data low byte

◆ TCS34725_CDATAH

#define TCS34725_CDATAH (0x15)

Clear channel data high byte

◆ TCS34725_RDATAL

#define TCS34725_RDATAL (0x16)

Red channel data low byte

◆ TCS34725_RDATAH

#define TCS34725_RDATAH (0x17)

Red channel data high byte

◆ TCS34725_GDATAL

#define TCS34725_GDATAL (0x18)

Green channel data low byte

◆ TCS34725_GDATAH

#define TCS34725_GDATAH (0x19)

Green channel data high byte

◆ TCS34725_BDATAL

#define TCS34725_BDATAL (0x1A)

Blue channel data low byte

◆ TCS34725_BDATAH

#define TCS34725_BDATAH (0x1B)

Blue channel data high byte

◆ TCS34725_INTEGRATIONTIME_2_4MS

#define TCS34725_INTEGRATIONTIME_2_4MS (0xFF)

Integration time settings for TCS34725 2.4ms - 1 cycle - Max Count: 1024

◆ TCS34725_INTEGRATIONTIME_24MS

#define TCS34725_INTEGRATIONTIME_24MS (0xF6)

24.0ms - 10 cycles - Max Count: 10240

◆ TCS34725_INTEGRATIONTIME_50MS

#define TCS34725_INTEGRATIONTIME_50MS (0xEB)

50.4ms - 21 cycles - Max Count: 21504

◆ TCS34725_INTEGRATIONTIME_60MS

#define TCS34725_INTEGRATIONTIME_60MS (0xE7)

60.0ms - 25 cycles - Max Count: 25700

◆ TCS34725_INTEGRATIONTIME_101MS

#define TCS34725_INTEGRATIONTIME_101MS (0xD6)

100.8ms - 42 cycles - Max Count: 43008

◆ TCS34725_INTEGRATIONTIME_120MS

#define TCS34725_INTEGRATIONTIME_120MS (0xCE)

120.0ms - 50 cycles - Max Count: 51200

◆ TCS34725_INTEGRATIONTIME_154MS

#define TCS34725_INTEGRATIONTIME_154MS (0xC0)

153.6ms - 64 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_180MS

#define TCS34725_INTEGRATIONTIME_180MS (0xB5)

180.0ms - 75 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_199MS

#define TCS34725_INTEGRATIONTIME_199MS (0xAD)

199.2ms - 83 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_240MS

#define TCS34725_INTEGRATIONTIME_240MS (0x9C)

240.0ms - 100 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_300MS

#define TCS34725_INTEGRATIONTIME_300MS (0x83)

300.0ms - 125 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_360MS

#define TCS34725_INTEGRATIONTIME_360MS (0x6A)

360.0ms - 150 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_401MS

#define TCS34725_INTEGRATIONTIME_401MS (0x59)

400.8ms - 167 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_420MS

#define TCS34725_INTEGRATIONTIME_420MS (0x51)

420.0ms - 175 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_480MS

#define TCS34725_INTEGRATIONTIME_480MS (0x38)

480.0ms - 200 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_499MS

#define TCS34725_INTEGRATIONTIME_499MS (0x30)

499.2ms - 208 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_540MS

#define TCS34725_INTEGRATIONTIME_540MS (0x1F)

540.0ms - 225 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_600MS

#define TCS34725_INTEGRATIONTIME_600MS (0x06)

600.0ms - 250 cycles - Max Count: 65535

◆ TCS34725_INTEGRATIONTIME_614MS

#define TCS34725_INTEGRATIONTIME_614MS (0x00)

614.4ms - 256 cycles - Max Count: 65535

Enumeration Type Documentation

◆ tcs34725Gain_t

enum tcs34725Gain_t

Gain settings for TCS34725

Enumerator
TCS34725_GAIN_1X	No gain
TCS34725_GAIN_4X	4x gain
TCS34725_GAIN_16X	16x gain
TCS34725_GAIN_60X	60x gain

Classes

Macros

Enumerations