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Adafruit Si5351 Library
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SI5351 class. More...
#include <Adafruit_SI5351.h>
Public Member Functions | |
| Adafruit_SI5351 (void) | |
| SI5351 object. More... | |
| err_t | begin (TwoWire *theWire=&Wire) |
| Initializes I2C and configures the breakout (call this function before doing anything else) More... | |
| err_t | setClockBuilderData (void) |
| Configures the Si5351 with config settings generated in ClockBuilder. You can use this function to make sure that your HW is properly configure and that there are no problems with the board itself. More... | |
| err_t | setupPLL (si5351PLL_t pll, uint8_t mult, uint32_t num, uint32_t denom) |
| Sets the multiplier for the specified PLL. More... | |
| err_t | setupPLLInt (si5351PLL_t pll, uint8_t mult) |
| Sets the multiplier for the specified PLL using integer values. More... | |
| err_t | setupPLLSource (si5351PLL_t pll, si5351PLLSource_t source, si5351ClkinDiv_t clkinDiv=SI5351_CLKIN_DIV_1) |
| Selects the reference source (XTAL or CLKIN) for the specified PLL, and optionally sets the CLKIN pre-divider. More... | |
| err_t | setupMultisynth (uint8_t output, si5351PLL_t pllSource, uint32_t div, uint32_t num, uint32_t denom) |
| Configures the Multisynth divider, which determines the output clock frequency based on the specified PLL input. More... | |
| err_t | setupMultisynthInt (uint8_t output, si5351PLL_t pllSource, uint8_t div) |
| Configures a Multisynth divider in integer mode. More... | |
| err_t | enableSpreadSpectrum (bool enabled) |
| Enables or disables spread spectrum. More... | |
| err_t | enableOutputs (bool enabled) |
| Enables or disables all clock outputs. More... | |
| err_t | readDeviceStatus (uint8_t *device_status) |
| Read register 0 status byte. More... | |
| err_t | readStickyStatus (uint8_t *sticky) |
| Read register 1 sticky byte. More... | |
| err_t | clearStickyStatus (void) |
| Clear register 1 sticky flags. More... | |
| err_t | setInterruptMask (uint8_t mask) |
| Write register 2 interrupt mask byte. More... | |
| err_t | setupRdiv (uint8_t output, si5351RDiv_t div) |
| Configures the R divider for a given output channel. More... | |
| err_t | setFrequency (uint8_t output, si5351PLL_t pll, uint32_t freq) |
| Automatically computes and applies the PLL multiplier, Multisynth divider and R divider needed to generate a desired output frequency on a given channel, then configures the hardware. This is a convenience wrapper over setupPLL(), setupMultisynth() and setupRdiv(). More... | |
SI5351 class.
| Adafruit_SI5351::Adafruit_SI5351 | ( | void | ) |
SI5351 object.
Constructor
| err_t Adafruit_SI5351::begin | ( | TwoWire * | theWire = &Wire | ) |
Initializes I2C and configures the breakout (call this function before doing anything else)
| theWire | The I2C (Wire) bus to use. |
| err_t Adafruit_SI5351::setClockBuilderData | ( | void | ) |
Configures the Si5351 with config settings generated in ClockBuilder. You can use this function to make sure that your HW is properly configure and that there are no problems with the board itself.
Running this function should provide the following output: Channel 0: 120.00 MHz Channel 1: 12.00 MHz Channel 2: 13.56 MHz
| err_t Adafruit_SI5351::setupPLL | ( | si5351PLL_t | pll, |
| uint8_t | mult, | ||
| uint32_t | num, | ||
| uint32_t | denom | ||
| ) |
Sets the multiplier for the specified PLL.
| pll | The PLL to configure, which must be one of the following:
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| mult | The PLL integer multiplier (must be between 15 and 90) |
| num | The 20-bit numerator for fractional output (0..1,048,575). Set this to '0' for integer output. |
| denom | The 20-bit denominator for fractional output (1..1,048,575). Set this to '1' or higher to avoid divider by zero errors. |
fVCO is the PLL output, and must be between 600..900MHz, where:
fVCO = fXTAL * (a+(b/c))
fXTAL = the crystal input frequency a = an integer between 15 and 90 b = the fractional numerator (0..1,048,575) c = the fractional denominator (1..1,048,575)
NOTE: Try to use integers whenever possible to avoid clock jitter (only use the a part, setting b to '0' and c to '1').
See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
| err_t Adafruit_SI5351::setupPLLInt | ( | si5351PLL_t | pll, |
| uint8_t | mult | ||
| ) |
Sets the multiplier for the specified PLL using integer values.
| pll | The PLL to configure, which must be one of the following:
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| mult | The PLL integer multiplier (must be between 15 and 90) |
| err_t Adafruit_SI5351::setupPLLSource | ( | si5351PLL_t | pll, |
| si5351PLLSource_t | source, | ||
| si5351ClkinDiv_t | clkinDiv = SI5351_CLKIN_DIV_1 |
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| ) |
Selects the reference source (XTAL or CLKIN) for the specified PLL, and optionally sets the CLKIN pre-divider.
| pll | The PLL whose reference source is being configured:
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| source | Reference source for this PLL:
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| clkinDiv | CLKIN pre-divider (reg 15, bits [7:6]). The CLKIN input to the PLLs must be in the 10..40 MHz range; pick a divider that brings your CLKIN signal into that window. Only written when source == SI5351_PLL_SOURCE_CLKIN, so that switching one PLL back to XTAL does not clobber the divider used by the other PLL.
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Register 15 – PLL Input Source
Bit | Field ---—+--------------------------------— 7:6 | CLKIN_DIV[1:0] 5:4 | (reserved) 3 | PLLB_SRC (0 = XTAL, 1 = CLKIN) 2 | PLLA_SRC (0 = XTAL, 1 = CLKIN) 1:0 | (reserved)
Both PLLA_SRC and PLLB_SRC are single-bit fields, so we use Adafruit_BusIO_RegisterBits to read-modify-write only the affected bit and leave the other PLL's source (and the reserved bits) intact.
| err_t Adafruit_SI5351::setupMultisynth | ( | uint8_t | output, |
| si5351PLL_t | pllSource, | ||
| uint32_t | div, | ||
| uint32_t | num, | ||
| uint32_t | denom | ||
| ) |
Configures the Multisynth divider, which determines the output clock frequency based on the specified PLL input.
| output | The output channel to use (0..2) |
| pllSource | The PLL input source to use, which must be one of:
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| div | The integer divider for the Multisynth output. If pure integer values are used, this value must be one of:
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| num | The 20-bit numerator for fractional output (0..1,048,575). Set this to '0' for integer output. |
| denom | The 20-bit denominator for fractional output (1..1,048,575). Set this to '1' or higher to avoid divide by zero errors. |
The multisynth dividers are applied to the specified PLL output, and are used to reduce the PLL output to a valid range (500kHz to 160MHz). The relationship can be seen in this formula, where fVCO is the PLL output frequency and MSx is the multisynth divider:
fOUT = fVCO / MSx
Valid multisynth dividers are 4, 6, or 8 when using integers, or any fractional values between 8 + 1/1,048,575 and 900 + 0/1
The following formula is used for the fractional mode divider:
a + b / c
a = The integer value, which must be 4, 6 or 8 in integer mode (MSx_INT=1) or 8..900 in fractional mode (MSx_INT=0). b = The fractional numerator (0..1,048,575) c = The fractional denominator (1..1,048,575)
| err_t Adafruit_SI5351::setupMultisynthInt | ( | uint8_t | output, |
| si5351PLL_t | pllSource, | ||
| uint8_t | div | ||
| ) |
Configures a Multisynth divider in integer mode.
Outputs 0..5 use the full fractional MultiSynths driven in integer mode (num=0, denom=1). Outputs 6 and 7 are hardware integer-only MultiSynths controlled by a single divider register each (regs 90/91), and are handled separately here.
| output | The output channel to configure (0..7). |
| pllSource | The PLL input source to use, which must be one of:
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| div | The integer divider. For CLK0..CLK5 use one of SI5351_MULTISYNTH_DIV_4/6/8. For CLK6/CLK7 use an even value in the range 6..254. |
| err_t Adafruit_SI5351::enableSpreadSpectrum | ( | bool | enabled | ) |
Enables or disables spread spectrum.
| enabled | Whether spread spectrum output is enabled |
| err_t Adafruit_SI5351::enableOutputs | ( | bool | enabled | ) |
Enables or disables all clock outputs.
| enabled | Whether output is enabled |
| err_t Adafruit_SI5351::readDeviceStatus | ( | uint8_t * | device_status | ) |
Read register 0 status byte.
Reads the current device status register.
| device_status | Pointer to where register 0 value will be stored. |
| err_t Adafruit_SI5351::readStickyStatus | ( | uint8_t * | sticky | ) |
Read register 1 sticky byte.
Reads the sticky interrupt status register.
| sticky | Pointer to where register 1 value will be stored. |
| err_t Adafruit_SI5351::clearStickyStatus | ( | void | ) |
Clear register 1 sticky flags.
Clears all sticky interrupt flags.
| err_t Adafruit_SI5351::setInterruptMask | ( | uint8_t | mask | ) |
Write register 2 interrupt mask byte.
Sets the interrupt status mask register.
| mask | Register 2 bitmask where 1 masks (disables) an interrupt source. |
| err_t Adafruit_SI5351::setupRdiv | ( | uint8_t | output, |
| si5351RDiv_t | div | ||
| ) |
Configures the R divider for a given output channel.
| output | Enables or disables output |
| div | Set of output divider values (2^n, n=1..7) |
The R divider provides a final power-of-two division stage (1..128) after the Multisynth, extending the usable output range down to low frequencies. It is a 3-bit field occupying bits 4..6 of the channel's MSx_PARAMETERS_3 register. The shifted value is cached in lastRdivValue[] so setupMultisynth() can preserve it when rewriting the same parameter byte.
| output | The output channel to configure (0..5). |
| div | The R divider value, one of:
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| err_t Adafruit_SI5351::setFrequency | ( | uint8_t | output, |
| si5351PLL_t | pll, | ||
| uint32_t | freq | ||
| ) |
Automatically computes and applies the PLL multiplier, Multisynth divider and R divider needed to generate a desired output frequency on a given channel, then configures the hardware. This is a convenience wrapper over setupPLL(), setupMultisynth() and setupRdiv().
| output | The output channel to use (0..2). |
| pll | The PLL to drive this output, either SI5351_PLL_A or SI5351_PLL_B. The caller selects the PLL; note that any other output already sharing this PLL will be retuned. |
| freq | Desired output frequency in Hz (8000 .. 150000000). |
The output is generated as:
fOUT = (fXTAL * (M)) / (D * R)
where fXTAL is the 25 MHz reference, M = a + b/c is the fractional PLL feedback multiplier, D is the (integer) Multisynth divider and R is the output R divider (1..128). To keep output jitter low the fractional part is placed entirely on the PLL while the Multisynth runs in integer mode.
The solver:
1.8.13